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Publications

International Journal (*Corresponding Author)

  1. Pen-Jui Peng*, Yan-Ting Chen, Sheng-Tsung Lai, and Hsiang-En Huang, “A 112Gb/s PAM-4 Voltage-Mode Transmitter with Four-Tap Two-Step FFE and Automatic Phase Alignment Techniques in 40nm CMOS,” IEEE Journal of Solid-State Circuits (JSSC), vol. 56, pp. 2123-2131, Jul. 2021.

  2. Jri Lee*, Ping-Chuan Chiang, Pen-Jui Peng, Li-Yang Chen, and Chih-Chi Weng, “Design of 56 Gb/s NRZ and PAM4 SerDes transceivers in CMOS technologies,” IEEE Journal of Solid-State Circuits (JSSC), vol. 50, pp. 2061-2073, Sep. 2015.

  3. Pen-Jui Peng, Pang-Ning Chen, Chiro Kao, Yu-Lun Chen, and Jri Lee*, “A 94GHz 3D image radar engine with 4TX/4RX beamforming scan technique in 65-nm CMOS technology,” IEEE Journal of Solid-State Circuits (JSSC), vol. 50, pp. 656-668, Mar. 2015.

  4. Jing-Lin Kuo, Yi-Fong Lu, Ting-Yi Huang, Yi-Long Chang, Yi-Keng Hsieh, Pen-Jui Peng, I.-Chih Chang, Tzung-Chuen Tsai, Kun-Yao Kao, Wei-Yuan Hsiung, James Wang, Yungping Alvin Hsu, Kun-You Lin, Hsin-Chia Lu, Yi-Cheng Lin, Liang-Hung Lu, Tian-Wei Huang, Ruey-Beei Wu, and Huei Wang*, “60-GHz four-element phased-array transmit/receive system-in-package using phase compensation techniques in 65-nm flip-chip CMOS process,” IEEE Transactions on Microwave Theory and Techniques, vol. 60, no. 3, pp. 743-756, Mar. 2012.

 

International Conference (*Corresponding Author)

  1. Pen-Jui Peng*, Sheng-Tsung Lai, Wei-Hung Wang, Chiang-Wei Lin, Wei-Chien Huang, Ted Shih, “A 100Gb/s NRZ Transmitter with 8-Tap FFE Using a 7b DAC in 40nm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2020, pp.130-131.

  2. Pen-Jui Peng*, Hsiang-En Huang, “A 30GHz Low-Phase-Noise Frequency Synthesizer in Sub-harmonic Direct-conversion System for IEEE 802.11ad Application,” in IEEE International Conference on Applied System Invention (ICASI), Nov. 2020.

  3. Pen-Jui Peng*, Yan-Ting Chen, Sheng-Tsung Lai, Chao-Hsuan Chen, Hsiang-En Huang, Ted Shih, “A 112Gb/s PAM-4 Voltage-Mode Transmitter with 4-Tap Two-Step FFE and Automatic Phase Alignment Techniques in 40nm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2019, pp.124-125.

  4. Pen-Jui Peng*, Yan-Ting Chen, Chao-Hsuan Chen, Sheng-Tsung Lai, Hsiang-En Huang, Ho-Hsuan Lu, Tsai-Chin Yu, “A 50-Gb/s Quarter-Rate Voltage-Mode Transmitter with Three-Tap FFE in 40-nm CMOS,” Digest of European Solid-State Circuits Conference (ESSCIRC), Sep. 2018, pp.174-177.

  5. Pen-Jui Peng, Jeng-Feng Li, Li-Yang Chen, and Jri Lee*, “A 56Gb/s PAM-4/NRZ Transceiver in 40nm CMOS," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2017, pp.110-111.

  6. Li-Yang Chen, Pen-Jui Peng, Chiro Kao, Yu-Lun Chen, and Jri Lee*, “CW/FMCW/Pulse Radar Engines for 24/26GHz Multi-Standard Applications in 65nm CMOS,” Digest of Asian Solid-State Circuits Conference (ASSCC), Nov. 2015, pp.1-4.

  7. Pen-Jui Peng, Chiro Kao, Chin-Yang Wu, and Jri Lee*, “A 79-GHz bidirectional pulse radar system with injection-regenerative receiver in 65nm CMOS,” in IEEE RFIC Symp. Dig., Jun. 2014, pp. 303-306.

  8. Yu-Lun Chen, Chiro Kao, Pen-Jui Peng, and Jri Lee*, “A 94GHz duobinary keying wireless transceiver in 65nm CMOS,” in Proc. IEEE Symp. VLSI Circuits, Jun. 2014, pp. 154-155.

  9. Pang-Ning Chen, Pen-Jui Peng, Chiro Kao, Yu-Lun Chen, and Jri Lee*, “A 94GHz 3D image radar engine with 4TX/4RX beamforming scan technique in 65nm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2013, pp. 146-147.

  10. Pen-Jui Peng, Jui-Chih Kao, and Huei Wang*, “A 57–66 GHz vector sum phase shifter with low phase/amplitude error using a Wilkinson power divider with LHTL/RHTL elements,” in IEEE CSIC Symp. Dig., Oct. 2011, pp. 1-4.

 

Local Conference (*Corresponding Author)

  1. Wen-Yu Hsiao, Pen-Jui Peng*, “A 32-Gb/s Clock Recovery Circuit using a Quarter-Rate Linear Phase Detector with High-Speed Tailless Current-Mode Logics,” in VLSI Design/CAD Symposium, Taichung, Taiwan, Aug. 4-7, 2020.

  2. Yan-Ting Chen, Sheng-Tsung Lai, Pen-Jui Peng*, “A 56-Gb/s Quarter-Rate Voltage-Mode Transmitter with Dual-Mode 3-Tap FFE in 40-nm CMOS Technology,” in VLSI Design/CAD Symposium, Taichung, Taiwan, Aug. 4-7, 2020.

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Patent

  1. Jri Lee, Pen-Jui Peng and Pang-Ning Chen, “Radio frequency transmitting device and radio frequency receiving device,” U.S. Patent No. 9,154,167.

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